This invention relates to an n-channel MOSFET having an STI (Shallow Trench Isolation) structure and a method for manufacturing the same, and more particularly to the improvement of the kink characteristic of an n-channel MOSFET.
Recently, in order to attain the high integration density and high performance of an LSI by miniaturizing elements, an element isolation insulating film of STI structure has been often used instead of an element isolation insulating film formed by the LOCOS (Local Oxidation Of Silicon) method which has been conventionally widely used.
(a) In the LOCOS method, since an SiO.sub.2 film is formed on the element isolation region by thermal oxidation while a film such as an Si.sub.3 N.sub.4 film having good resistance to oxidation is used as a mask, it becomes difficult to enhance the insulation property thereof in the depth direction by making the element isolation film thick and it is impossible to attain a sufficiently long effective element isolation distance owing to miniaturization, and (b) since oxidation proceeds in the end portion of the element isolation region in the thermal oxidation process, a field bird's beak is formed to act as a troublesome obstacle to the miniaturization. On the other hand, in the STI structure, (c) since the pattern dimension is determined by the normal photo-etching process and anisotropic dry etching process, a fine pattern dimension can be attained by use of the high processing technology, and (d) since a long effective element isolation distance can be easily attained in the depth direction by forming a deep trench, for example, it is more advantageous for miniaturization in comparison with the element isolation insulating film formed by the LOCOS method. By the above reasons, in the recent LSI, the element isolation region is formed with the STI structure which is advantageous for miniaturization.
As one example of a conventional semiconductor device having the above STI structure, an n-channel MOSFET and a manufacturing method therefor are explained. FIG. 1A is a pattern view, FIG. 1B is a cross sectional view taken along the 1B--1B line of FIG. 1A and FIG. 1C is a cross sectional view taken along the 1C--1C line of FIG. 1A. A p-well region 12 is formed in the main surface portion of a p-type Si substrate 11. In the p-well region 12, n.sup.+ -type diffusion layers used as source/drain regions 13 of the n-channel MOSFET are separately formed. A trench is formed in the main surface portion of the p-type Si substrate 11 and an oxide film (buried oxide film) 14 is filled in the trench to form an element isolation region of STI structure. A gate insulating film 15 is formed on a portion of the substrate 11 which lies between the source and drain regions 13 and a gate electrode 16 is formed on the gate insulating film. An inter-level insulating film (SiO.sub.2 /BPSG) 17 is formed on the main surface of the substrate 11. Contact plugs 18 are formed in contact holes formed in portions of the inter-level insulating film 17 which correspond to the source/drain regions 13. Metal wirings used as source/drain electrodes 19 are formed on the inter-level insulating film 17. The source/drain electrodes 19 are electrically connected to the source/drain regions 13 via the contact plugs 18, respectively.
Next, a manufacturing method of the n-channel MOSFET shown in FIGS. 1A, 1B and 1C is explained. FIGS. 2A to 8A are cross sectional views showing the cross sections taken along the 1B--1B line of FIG. 1A in the order of the manufacturing steps. FIGS. 2B to 8B are cross sectional views showing the cross sections taken along the 1C--1C line of FIG. 1A in the order of the manufacturing steps. First, as shown in FIGS. 2A and 2B, the main surface of the p-type Si substrate 11 is subjected to the thermal oxidation process to form an SiO.sub.2 film (buffer film) 21 with a thickness of 10 nm, for example. Then, a polycrystalline Si film 22 with a thickness of approx. 200 nm is deposited and formed on the above film by the LP-CVD method. Further, an SiO.sub.2 film 23 with a thickness of 200 nm is deposited and formed on the above film 22 by the LP-CVD method. Next, a mask (resist pattern) 24 corresponding to the element region is formed on the SiO.sub.2 film 23 by the photo-etching process. The SiO.sub.2 film 23 is etched by the anisotropic dry etching process having a large selective etching ratio with respect to polycrystalline Si with the resist pattern 24 used as a mask.
After this, the resist pattern 24 is separated. Then, the polycrystalline Si film 22 is etched by the anisotropic dry etching process having a sufficiently large selective etching ratio with respect to an oxide film with the remaining SiO.sub.2 film 23 used as a mask, further the thermal oxide film (SiO.sub.2 film) 21 is etched, and as a result, the structure shown in FIGS. 3A and 3B is obtained.
After this, the Si substrate 11 is etched to the depth of approx. 0.5 .mu.m by the anisotropic dry etching process having a sufficiently large selective etching ratio with respect to an oxide film so as to form a trench 25 used for forming the STI structure as shown in FIGS. 4A and 4B.
Then, an SiO.sub.2 film 14 is deposited and formed to the thickness of approx. 1.5 .mu.m on the entire surface of the resultant semiconductor structure by the LP-CVD method. Next, the SiO.sub.2 film 14 is made flat by the CMP (Chemical Mechanical Polishing) method having a preset selective etching ratio with respect to polycrystalline Si. After the planarization process, the SiO.sub.2 films 14, 23 are etched by use of NH.sub.4 F or by the dry etching process until the main surface of the polycrystalline Si film 22 is just exposed. As a result, the SiO.sub.2 film is left behind in the trench 25 and the buried oxide film 14 is formed (refer to FIGS. 5A and 5B).
Next, the polycrystalline Si film 22 is etched and removed by the isotropic dry etching process having a sufficiently large selective etching ratio with respect to SiO.sub.2 and then the heat treatment for reducing the film stress of the buried oxide film 14 is effected at a temperature of 1000.degree. C., for example. After this, the SiO.sub.2 film 21 on the Si substrate 11 is removed by the etching process using NH.sub.4 F and a new SiO.sub.2 film (sacrificial oxide film) 26 is formed on the Si substrate 11 by the thermal oxidation process at a temperature of 800.degree. C., for example. Then, boron (B) is implanted with, for example, the acceleration energy 200 keV and the dose amount of approx. 8.times.10.sup.12 cm.sup.-2 in order to form a p-well region 12 and boron (B) is further implanted in a condition that, for example, the acceleration energy is 50 keV and the dose amount is approx. 1.times.10.sup.13 cm.sup.-2 in order to control the threshold voltage of the n-channel MOSFET. Next, the heat treatment is effected at 1000.degree. C. for 30 seconds to activate the doped impurity (FIGS. 6A and 6B).
Further, the sacrificial oxide film 26 on the surface of the Si substrate 11 is removed and the surface of the Si substrate 11 is thermally oxidized at a temperature of 750.degree. C. to form a gate oxide film 15 with a thickness of 6 nm. Then, polycrystalline Si is deposited to 300 nm on the entire surface of the gate oxide film 15 by the LP-CVD method. A mask (resist pattern) 27 used for forming a gate electrode is formed by the photo-etching process and the polycrystalline Si film is patterned by the anisotropic dry etching process having a sufficiently large selective etching ratio with respect to SiO.sub.2 with the resist pattern 27 used as a mask to form a gate electrode 16 (FIGS. 7A and 7B).
After this, arsenic (As) is ion-implanted into the Si substrate 11 in a condition that, for example, the acceleration energy is 50 keV and the dose amount is approx. 5.times.10.sup.15 cm.sup.-2 and the heat treatment is effected for approx. 30 seconds in an N.sub.2 atmosphere of 1000.degree. C. to form n.sup.+ -type diffusion layers used as the source/drain regions 13. At this time, since the ion-implantation process is effected with the gate electrode 16 used as a mask, the gate electrode 16 is also doped with impurity and becomes an n.sup.+ type (FIGS. 8A and 8B).
After this, the steps for forming an inter-level insulating film 17, forming contact holes, forming contact plugs 18 and forming source/drain electrodes 19 by preset metallization and the like are effected to form the n-channel MOSFET as shown in FIGS. 1A, 1B and 1C.
In the n-channel MOSFET having the element isolation region with STI structure formed therein, a kink characteristic appearing in the sub-threshold characteristic of the MOSFET as shown in FIG. 9 is a serious problem. As shown in FIG. 9, the kink characteristic exhibits a double characteristic curve in the sub-threshold region which is not observed in a normal MOSFET. As shown in FIG. 10A, it is considered that the sub-threshold characteristic occurs in an end portion 28 of the STI structure in the n-channel MOSFET and the reason is as follows.
(1) In the STI end portion, unlike the element isolation insulating film (refer to portions 29 indicated by broken lines) formed by the LOCOS method as shown in FIG. 10B, a sharp Si end is formed in contact with the channel region and the effective threshold voltage of part of the region is lowered by concentration of the electric field in the corner portion so as to cause the kink characteristic.
(2) The impurity in the Si substrate is out diffused into the insulating film region of STI structure by forming the STI structure and the effective threshold voltage of the channel region of the STI end portion is lowered. Particularly, in the STI structure, since area of the cross section which is formed in contact with the insulating film in the channel end portion becomes large with respect to the element isolation insulating film formed by the LOCOS method, it is easily influenced by the out diffusion. Therefore, the threshold voltage of the MOSFET in the STI end portion is locally lowered to cause the kink characteristic.
It is considered that the kink phenomenon of the MOSFET occurs by a combination of the above two reasons, but the kink phenomenon appears significantly in the n-channel MOSFET and is not observed in the p-channel MOSFET when the MOSFETs are formed by the CMOS process. This is because phosphorus (P) or arsenic (As) which piles up and is not out diffused with respect to the SiO.sub.2 film in the STI region is used as the impurity of the substrate region in the p-channel MOSFET. On the other hand, in the n-channel MOSFET, the problem occurs since boron (B) which tends to be out diffused into the STI region is used as the impurity of the substrate and boron is out diffused to lower the impurity concentration.
Thus, since the channel width is determined only by the STI end portion, the degree of the kink characteristic which is associated with the driving power of the MOSFET of this portion is as small as negligible. However, as is clearly understood from FIG. 9, since a large leak current which does not normally appear occurs, it becomes a great obstacle to miniaturization of elements and enhancement of the operation speed. If the high-speed operation of the LSI is taken into consideration, the lower limit of the leak current in the standby state is determined by the kink characteristic and the lower limit of the threshold voltage of the MOSFET in the LSI is determined by the threshold voltage given by a parasitic MOSFET, and therefore, the influence thereof is extremely large. If the threshold voltage of the parasitic MOSFET is lower by 0.2V than that of the normal MOSFET, the threshold voltage which is set at 0.5V in the case of the operation voltage of 2.5V must be set to 0.7V and it is predicted that the performance is lowered by approx. 10% when considering a current model of Shockley. Therefore, if a lowering in the power supply voltage with miniaturization is considered, the influence thereof becomes extremely large and it is necessary to improve the kink characteristic in both of the high integration density and high performance.
As described above, in the conventional MISFET having the STI structure, the kink characteristic is a serious problem. The kink characteristic is caused by the influence of concentration of the electric field or the like in the STI end portion, but if the threshold voltage of part of the STI end portion is effectively lowered, a parasitic MISFET having a lower threshold voltage is apparently formed and the leak current of the MISFET increases.